`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:54:25 02/29/2008 
// Design Name: 
// Module Name:    rhdl_pico_peripheral 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module rhdl_pico_peripheral(CLK_I, CLOCK1, READ_I, WRITE_I, ADDR_I, DATA_I, DATA_O, RESET_O, TEST_BUS_WRITE_O, TEST_BUS_READ_I
	`ifdef ENABLE_RAM_PADS, RAM_CLK_I, SYS_BUSY_I, SYS_DATA_OUT_I, SYS_DATA_IN_O, SYS_ADDR_O, SYS_WRITE_O, SYS_START_O `endif // ENABLE_RAM_PADS 
);
    input CLK_I;
	 input CLOCK1;
    input READ_I;
    input WRITE_I;
    input [31:0] ADDR_I;
    input [15:0] DATA_I;
    output [15:0] DATA_O;
    output RESET_O;
    output [12:0] TEST_BUS_WRITE_O;
    input [12:0] TEST_BUS_READ_I;    
	 
	 wire [12:0] test_bus;
    
    `ifdef ENABLE_RAM_PADS
		input RAM_CLK_I;
    	input SYS_BUSY_I;
    	input [31:0] SYS_DATA_OUT_I;
    	output [31:0] SYS_DATA_IN_O;
    	output [31:0] SYS_ADDR_O;
    	output SYS_WRITE_O;
    	output SYS_START_O;
    `endif

    
    
    wire main_clk_en;
    wire main_clk;
    wire main_reset;
    wire main_write;
    
    wire [15:0] data_ctl_o;
    wire [15:0] data_io_o;	 
    
    wire [15:0] read_data;
    wire [12:0] write_data;
    wire [12:0] write_addr;
    wire [13:0] read_addr;
	 	
	 wire [15:0] fifo_to_bus;
	 wire [17:0] fifo_from_bus;
	 wire fifo_write;
	 wire fifo_read;
	 wire [1:0] fifo_status;

	wire ram_write;
	wire ram_read;
	wire [63:0] ram_data_in;
	wire [41:0] ram_data_out;
	wire [1:0] ram_status;

    //BUFGCE ClockOutBuf(.I(RAM_CLK_I), .CE(main_clk_en), .O(main_clk)); 
	 BUFGCE ClockOutBuf(.I(CLOCK1), .CE(main_clk_en), .O(main_clk)); 
        
assign RESET_O = main_reset;
        
rhdl_pico_ctl rhdl_pico_ctlr (
    .CLK_I(CLK_I), 
    .READ_I(READ_I), 
    .WRITE_I(WRITE_I), 
    .ADDR_I(ADDR_I), 
    .DATA_I(DATA_I), 
    .MUX_DATA_I(read_data), 
    .CLK_EN_O(main_clk_en), 
    .RESET_O(main_reset), 
    .START_O(main_start),
    .WRITE_O(main_write), 
    .DATA_O(data_ctl_o), 
    .WRITE_ADDR_O(write_addr),
    .READ_ADDR_O(read_addr), 
    .WRITE_DATA_O(write_data)
    );

rhdl_pico_io rhdl_io (
    .BUS_CLK_I(CLK_I), 
    .RHDL_CLK_I(main_clk), 
    .RESET_I(main_reset), 
    .READ_I(READ_I), 
    .WRITE_I(WRITE_I), 
    .ADDR_I(ADDR_I), 
    .DATA_I(DATA_I), 
    .WRITE_FIFO_I(fifo_write), 
    .READ_FIFO_I(fifo_read), 
    .FIFO_DATA_I(fifo_to_bus), 
    .DATA_O(data_io_o), 
    .FIFO_DATA_O(fifo_from_bus),
	 .FIFO_STATUS_O(fifo_status)
	 //.TEST_BUS_O(test_bus)
    );

	     
rhdl_ExternalInterfaceComponent rhdl_interface (
	.MAIN_READ_ADDR_I(read_addr),
    .MAIN_CLK_I(main_clk), 
    .MAIN_RESET_I(main_reset), 
    .MAIN_WRITE_ADDR_I(write_addr), 
    .MAIN_WRITE_I(main_write), 
    .MAIN_START_I(main_start), 
    .MAIN_DATA_I(write_data), 
    .MAIN_DATA_O(read_data),
	 .FIFO_O(fifo_to_bus),
	 .FIFO_I(fifo_from_bus),
	 .FIFO_WRITE_O(fifo_write),
	 .FIFO_READ_O(fifo_read),
	 .FIFO_STATUS_I(fifo_status),
	 .RAM_O(ram_data_in),
	 .RAM_I(ram_data_out),
	 .RAM_WRITE_O(ram_write),
	 .RAM_READ_O(ram_read),
	 .RAM_STATUS_I(ram_status),
    .TEST_BUS_WRITE_O(TEST_BUS_WRITE_O),
    .TEST_BUS_READ_I(test_bus)
);
  //`ifdef ENABLE_RAM_PADS									    

rhdl_pico_sdram_io rhdl_sdram_io (
    .MEM_CLK_I(RAM_CLK_I), 
    .RHDL_CLK_I(main_clk), 
    .RESET_I(RESET_I), 
    .WRITE_FIFO_I(ram_write), 
    .READ_FIFO_I(ram_read), 
    .FIFO_DATA_I(ram_data_in), 
    .FIFO_DATA_O(ram_data_out), 
    .FIFO_STATUS_O(ram_status),     
	 .TEST_BUS_O(test_bus), 
    .SYS_BUSY_I(SYS_BUSY_I), 
    .SYS_DATA_I(SYS_DATA_OUT_I), 
    .SYS_DATA_O(SYS_DATA_IN_O), 
    .SYS_ADDR_O(SYS_ADDR_O), 
    .SYS_WRITE_O(SYS_WRITE_O), 
    .SYS_START_O(SYS_START_O)
    );
//`endif

   
    /*
io_test io_test (
    .CLK_I(CLK_I), 
    .READ_I(READ_I), 
    .WRITE_I(WRITE_I), 
    .ADDR_I(ADDR_I), 
    .DATA_I(DATA_I), 
    .DATA_O(DATA_O)
    );
*/

	assign DATA_O = data_io_o | data_ctl_o;    
endmodule
